YOSHIMURA Tsutomu

写真a

Title

Professor

Research Fields, Keywords

integrated circuit, analog integrated circuit, high-speed serial interface, phase-locked loop circuit

Graduating School 【 display / non-display

  • The University of Tokyo   Faculty of Liberal Arts   JAPAN

Graduate School 【 display / non-display

  • Hiroshima University    semiconductor electronics & integration science  Doctor's Course  Completed  JAPAN

  • The University of Tokyo  Graduate School, Division of Science  Master's Course  Completed  JAPAN

Degree 【 display / non-display

  • Hiroshima University -  Ph. D  Electron device/Electronic equipment

Association Memberships 【 display / non-display

  • 2005.04
    -
    Now
     

    IEEE  Others

  • 2007.04
    -
    Now
     

    IEICE  Others

  • 2007.09
    -
    Now
     

    IEEJ  JAPAN

Committee Memberships 【 display / non-display

  • 2016.06
    -
    2020.06

     

Research field 【 display / non-display

  • integrated circuit design

 

Research Career 【 display / non-display

  • Reduction of jitter caused by interference noise in phase-locked loop circuits

    Project Year:2016.04  -  Now 

    closed-loop control, PLL, interference noise, phase noise, self-injection

    Individual

  • A study of interference in phase-locked loops

    Project Year:2013.04  -  2016.03 

    phase-locked loop, phase noise, interference

  • Study of self-startup boost converter for thermoelectric energy harvesting

    Project Year:2016.04  -  Now 

    Boost converter, energy harvesting, low supply voltage circuit

    Individual

  • Study of low phase noise and wide pull-in range subharmonically injection-locked PLL

    Project Year:2016.04  -  2019.03 

    injection locking, phse-locked loop circuit, phase noise

    Individual

  • A study of optimaization for efficiency and power control in electromagnetic WPT system

    Project Year:2013.04  -  2015.03 

    magnetic resonance, wireless power transfer system, feedback system

Papers 【 display / non-display

  • Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers

    Takao Kihara, Tomoya Takahashi, Tsutomu Yoshimura  ( Multiple Authorship )

    IEEEE Transactions on Circuits and Systems I   66 ( 6 ) 2007 - 2016   2019.06

    Research paper (scientific journal)  English

  • Study of mutual injection pulling in a 5-GHz, 0.18-um CMOS cascaded PLL

    Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, and Tsutomu Yoshimura  ( Multiple Authorship )

    IEEE Asia Pacific Conference on Circuits and Systems     2018.10

    Research paper (international conference proceedings)  English

  • Analysis and modeling of response of external noise in oscillators

    Takao Kihara  ( Multiple Authorship )

    Analog Integrated Circuits and Signal Processing   87 ( 2 ) 313 - 325   2016.05

    Research paper (scientific journal)  English

  • Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop

    S. Iwade, H. Makino, and Y. Matsuda  ( Multiple Authorship )

    IEEE Transactions on Circuits and Ststems I, (TCAS-I)   60 ( 4 ) pp. 896 - 907   2014.04

    Research paper (scientific journal)  English

Industrial Property 【 display / non-display

  • mutual injection-locked PLL circuit

    Patent

    Application number:2018-141815 

    Yoshimura Tsutomu

    Applicant country:JAPAN  Application Date:2018.07.27 

Research Grants and Projects 【 display / non-display

  • Project Year:2019.04  -  2022.03 

  • Project Year:2013.04  -  2016.03 

Presentations 【 display / non-display

  • Study of mutual injection pulling in a 5-GHz, 0.18-um CMOS cascaded PLL

    Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, and Tsutomu Yoshimura

    International conference  IEEE Asia Pacific Conference on Circuits and Systems  ( 中国、成都 )  Oral Presentation(general)

    2018.10
     
     

    【Proceedings】  175  -  178  2018.10

  • Spur reduction by self-injection loop in a fractional-N PLL

    Mayu Kobayashi

    International conference  24th IEEE International Conference on Electronics Circuits and Systems (ICECS)  ( Batumi, Georgia )  Oral Presentation(general)

    2017.12
     
     

    【Proceedings】  260  -  263  2017.12

  • A 2.6GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection

    藤居 尚博

    International conference  New Circuits and Systems Conference (NEWCAS)  Oral Presentation(general)

    2016.06
     
     

    【Proceedings】 IEEE International New Circuits and Systems Conference (NEWCAS)  1  -  4  2016.06

  • パルス幅を可変としたサブハーモニック注入同期PLL

    森下宗瑛

    International conference  International Symposium on Circuits and Systems (ISCAS)  Oral Presentation(general)

    2015.05
     
     

    【Proceedings】 IEEE International Symposium on Circuits and Systems (ISCAS)  557  -  560  2015.05

  • 発振器の干渉ノイズモデルの解析

    吉村 勉

    International conference  Oral Presentation(general)

    2014.12
     
     

    【Proceedings】 ICECS  128  -  131  2014.12

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