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Title |
Professor |
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Research Fields, Keywords |
integrated circuit, analog integrated circuit, high-speed serial interface, phase-locked loop circuit |
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Profile |
Tsutomu Yoshimura received the B.S. and M.S. degrees in physics from the University of Tokyo in 1989 and 1991, respectively and the Ph.D. degree in electrical engineering in 2005 from Hiroshima University. From 1993 to 2007, he was with Mitsubishi Electric Corporation, Itami, Japan, where he contributed toward the design of system LSIs for optical communication systems. Since 2007, he has been an Associate Professor and also a Professor of electrical and electronic systems engineering with Osaka Institute of Technology, Osaka, Japan. His interests are the design of high-speed analog and digital circuits, including phase-locked loop circuits. He is also interested in investigating the interference and coupling issues between closed-loop systems. He received the 2007 IEEE Circuits and Systems Society Darlington Best Paper Award. |
YOSHIMURA Tsutomu
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Graduating School 【 display / non-display 】
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The University of Tokyo Faculty of Liberal Arts JAPAN
Graduate School 【 display / non-display 】
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Hiroshima University semiconductor electronics & integration science Doctor's Course Completed JAPAN
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The University of Tokyo Graduate School, Division of Science Master's Course Completed JAPAN
Degree 【 display / non-display 】
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Hiroshima University - Ph. D Electron device/Electronic equipment
Association Memberships 【 display / non-display 】
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2005.04-Now
IEEE Others
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2007.04-Now
IEICE Others
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2007.09-Now
IEEJ JAPAN
Research Career 【 display / non-display 】
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Reduction of jitter caused by interference noise in phase-locked loop circuits
Project Year：2016.04 - Now
closed-loop control, PLL, interference noise, phase noise, self-injection
Individual
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Study of self-startup boost converter for thermoelectric energy harvesting
Project Year：2016.04 - Now
Boost converter, energy harvesting, low supply voltage circuit
Individual
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A study of interference in phase-locked loops
Project Year：2013.04 - 2016.03
phase-locked loop, phase noise, interference
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Study of low phase noise and wide pull-in range subharmonically injection-locked PLL
Project Year：2016.04 - 2019.03
injection locking, phse-locked loop circuit, phase noise
Individual
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A study of optimaization for efficiency and power control in electromagnetic WPT system
Project Year：2013.04 - 2015.03
magnetic resonance, wireless power transfer system, feedback system
Papers 【 display / non-display 】
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Investigation of a wide-bandwidth and low-spur Fractional-N PLL
Shunta Nakao, Tsutomu Yoshimura ( Multiple Authorship )
International Meeting for Future of Electron Devices, Kansai (IMFEDK) 2023.11
Research paper (international conference proceedings) English
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Analysis of the Electromagnetic Coupling of Two Phase-Locked Loops
Ryuji Komabayashi, Tsutomu Yoshimura ( Multiple Authorship )
IEEE International Symposium on Circuits and Systems (ISCAS) 2023.05
Research paper (international conference proceedings) English
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Self-coupling and mutual pulling in phase-locked loops
Tsutomu Yoshimura ( Single Author )
IEEE Transactions on circuits and systems I: Regular papers 69 ( 8 ) 3260 - 3271 2022.08
Research paper (scientific journal) English
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Mitigation of mutual pulling in two phase-locked loops
Tsutomu Yoshimura ( Single Author )
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) 2021.06
Research paper (international conference proceedings) English
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Study of Injection Pulling of Oscillators in Phase-Locked Loops
Tsutomu Yoshimura ( Single Author )
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 ( 2 ) 321 - 332 2021.02
Research paper (scientific journal) English
Industrial Property 【 display / non-display 】
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Fractional-N PLL circuit
Patent
Application number：2024-191156
Yoshimura Tsutomu
Applicant country：JAPAN Application Date：2024.10.30
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Injection-locked oscillators
Patent
Application number：特願2022-026047
Yoshimura Tsutomu
Applicant country：JAPAN Application Date：2022.02.22
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mutual injection-locked PLL circuit
Patent
Application number：2018-141815
Yoshimura Tsutomu
Applicant country：JAPAN Application Date：2018.07.27
Research Grants and Projects 【 display / non-display 】
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Project Year：2024.04 - 2027.03
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Project Year：2019.04 - 2022.03
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Project Year：2013.04 - 2016.03
Presentations 【 display / non-display 】
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Estimation of parameters in mutual coupled PLLs using genetic algorithm
International conference Poster (general)
2025.11 -
Spur reduction of Fractional-N PLL using pseudo reference clock
International conference Poster (general)
2025.11 -
Jitter tolerance evaluation in a CDR-PLL circuit with error detector
International conference Poster (general)
2025.11 -
Investigation of Fast Locking in Overclocking Fractional-N PLL
有馬 雄, 吉村 勉
International conference International Meeting for Future of Electron Devices, Kansai (IMFEDK) ( 京都 ) Poster (general)
2025.11 -
2.5Gbps CDR-PLL with Improved Phase Detector for Jitter Tolerance Enhancement
岡田 康宏, 吉村 勉
International conference International Meeting for Future of Electron Devices, Kansai (IMFEDK) ( 京都 ) Poster (general)
2024.11